Recent Study on Power Efficient Arithmetic Circuits for Low Power Applications

Low power consumption is required for integrated circuit design in nanometerscale CMOS technology.

Recent research shows that, when compared to accurate designs, implementing approximate designs results in lower power dissipation. DSP blocks have been used as the core blocks in the majority of multimedia applications. The majority of video and image processing algorithms are implemented by these DSP blocks, with the end result being an image or video for human viewing. Because the human sense of observation is limited, the output of the DSP blocks allows for numerical approximation rather than accuracy. Because of the numerical exactness concession, approximate analysis can be proposed. This project proposes approximate adders, approximate compressors, and approximate multipliers. Two approximate adders, PA1 and PA2, of type TGA, are proposed and provide better results, such as The PA1 has 14 transistors and 2 error distances, which results in a 64.9% delay reduction and a 74.33% power reduction, whereas the TGA1 has 16 transistors and more power dissipation. PA2 is made up of 20 transistors and two error distances. Similarly, PA2 reduces delay by 51.43% while decreasing power by 67.2%. PDP has been reduced by 61.97%, whereas TGA2 had 22 transistors. In this project, 4-2 compressor was proposed to reduce the number of partial products. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. An approximate 4x4 multiplier is proposed using the proposed adder and compressors. When compared to the accurate multiplier, the proposed multiplier achieves a delay of 124.56 (ns) and a power of 29.332 (uW), which is reduced by 68.01% of delay and 95.97% in terms of power.